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| CY25701 Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option Features * Crystal Oscillator with Spread Spectrum Clock (SSXO) * No Spread Spectrum (XO) Option * Wide operating output clock frequency range of 10-166 MHz * Programmable spread spectrum with nominal 31.5 kHz modulation frequency * Center spread: 0.25% to 2.0% * Down spread: -0.5% to -4.0% * No spread: 0.0% * Integrated phase-locked loop (PLL) * 85 ps typical cycle-to-cycle Jitter with SSCLK = 133 MHz * 3.3V operation * Output Enable function * Package available in 4-Pin Ceramic LCC SMD * Pb-free package * Industrial Temperature from -40C to 85C Benefits * Provides a wide range of spread percentages for maximum electromagnetic interference (EMI) reduction to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. * This versatile programming feature enables the user to switch between SSXO (with Spread) and XO (without Spread) functions with ease. * Internal PLL to generate up to 166 MHz output. * Suitable for most PC, consumer, and networking applications * Application compatibility in standard and low-power systems * In-house programming of samples and prototype quantities is available using CY3672 programming kit and CY3724 socket adapters. Production quantities are available through Cypress's value-added distribution partners or by using third-party programmers from BP Microsystems, HiLo Systems, and others. Logic Block Diagram Pin Configuration CY25701 RFB 4-pin Ceramic SMD PLL with MODULATION CONTROL 4 VDD 3 SSCLK CXIN PROGRAMMABLE CONFIGURATION CXOUT OUTPUT DIVIDERS and MUX 3 SSCLK OE 1 VSS 2 1 OE 4 VDD 2 VSS Cypress Semiconductor Corporation Document #: 001-07313 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 25, 2006 [+] Feedback CY25701 Pin Definition Pin 1 2 3 4 OE VSS SSCLK VDD Name Power supply ground Spread spectrum clock output (with or without spread) 3.3V power supply must be submitted to the local Cypress Field Application Engineer (FAE) or Sales Representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample request and the production orders. Contact your local Cypress FAE or sales representative for details. Additional information on the CY25701 can be obtained from the Cypress web site at www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing from the embedded crystal oscillator frequency input. The range of synthesized clock is from 10 to 166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread can be programmed to various spread percentage values from 0.25% to 2.0% for Center Spread and from -0.5% to -4.0% for Down Spread. Refer to Table 2 for available spread options. Enter 0.0% (No spread) for XO (Crystal Oscillator) without spread option. Frequency Modulation (SSCLK, pin 3) The default frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Alternate frequency modulations at 30.1 kHz or 32.9 kHz can be selected via Cyberclocks software. Contact the factory for other alternate modulation frequencies if required. Description Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled Functional Description The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO) IC used to reduce the EMI found in today's high-speed digital electronic systems. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25701 uses a programmable configuration memory array to synthesize output frequency and spread%. The spread% is programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.25% to 2.00%. The range for down spread is from -0.5% to -4.0%. Contact the factory for smaller or larger spread% amounts if required. Refer to Table 2 for spread selection and no-spread values. The frequency modulated SSCLK output can be programmed from 10 to 166 MHz. The CY25701 is available in a 4-pin ceramic SMD package with an operating temperature range of -40 to 85C. Programming Description Factory/Field Programmable CY25701 Factory/Field programming is available for samples and manufacturing by Cypress and its distributors. All requests Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency SSCLK 3 MHz ENTER DATA Spread Percent Code[1] SSCLK 3 % ENTER DATA Frequency Modulation SSCLK 3 kHz 31.5 Note 1. 0.0% or Code "Z" for XO (No-Spread) option. Document #: 001-07313 Rev. *A Page 2 of 8 [+] Feedback CY25701 Table 2. Spread Percent Selection Center Spread Down Spread Code Percentage Code Percentage A 0.25% G -0.5% B 0.5% H -1.0% C 0.75% J -1.5% D 1.0% K -2.0% E 1.5% L -3.0% F 2.0% M -4.0% Z 0.0% Z 0.0% Absolute Maximum Ratings Supply Voltage (VDD) .................................... -0.5V to +7.0V DC Input Voltage....................................-0.5V to VDD + 0.5V Storage Temperature (Non-condensing) .... -55C to +100C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C.................................>10 years Package Power Dissipation...................................... 350 mW Operating Conditions Parameter VDD TA TA CLOAD FSSCLK FMOD TPU Supply Voltage Ambient Temperature (Commercial) Ambient Temperature (Industrial) Max. Load Capacitance @ pin 3 SSCLK output frequency, CLOAD = 15 pF Spread Spectrum Modulation Frequency Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description Min. 3.00 -20 -40 - 10 30.0 0.05 Typ. 3.30 - - - - 31.5 - Max. 3.60 70 85 15 166 33.0 500 Unit V C C pF MHz kHz ms DC Electrical Characteristics Parameter IOH IOL VIH VIL IIH IIL IOZ CIN [2] Description Output High Current (pin 3) Output Low Current (pin 3) Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Current (pin 1) Input Low Current (pin 1) Output Leakage Current (pin 3) Input Capacitance (pin 1) Supply Current Initial Accuracy at room temp. Freq. Stability over temp. range Aging Condition VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD= 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Vin = VDD Vin = VSS Three-state output, OE = 0 Pin 1, or OE VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD TA = 25C, 3.3V TA = -20C to 70C, 3.3V TA = 25C, First year Min. 10 10 0.7VDD - - - -10 - - -25 -25 -12 -5 Typ. 12 12 - - - - - 5 - - - - - Max. - - VDD 0.3VDD 10 10 10 7 50 25 25 12 5 Unit mA mA V V A A A pF mA ppm ppm ppm ppm IVDD f/f Freq. Stability over voltage range 3.0 to 3.6V Note 2. Guaranteed by characterization, not 100% tested. Document #: 001-07313 Rev. *A Page 3 of 8 [+] Feedback CY25701 AC Electrical Characteristics[2] Parameter DC tR tF TCCJ1[3] Description Output Duty Cycle Output Rise Time Output Fall Time Condition SSCLK, Measured at VDD/2 20%-80% of VDD, CL = 15 pF 20%-80% of VDD, CL = 15 pF 25 MHz SSCLK <133 MHz, Measured at VDD/2 SSCLK < 25 MHz, Measured at VDD/2 Min. 45 - - - - - - - - Typ. 50 - - 85 215 - 150 150 - Max. 55 2.7 2.7 200 400 1% of 1/SSCK 350 350 10 Unit % ns ns ps ps s ns ns ms Cycle-to-Cycle Jitter SSCLK (Pin 3) SSCLK 133 MHz, Measured at VDD/2 TOE1 TOE2 TLOCK Output Disable Time (pin1 = OE) Output Enable Time (pin1 = OE) PLL Lock Time Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for SSCLK to reach valid frequency Application Circuit Figure 1. Application Circuit Diagram Power 4 VDD 0.1 F 3 SSCLK CY25701 OE 1 VSS 2 VDD Note 3. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer to the application note, "Jitter in PLL Based Systems: Causes, Effects, and Solutions" available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer. Document #: 001-07313 Rev. *A Page 4 of 8 [+] Feedback CY25701 Switching Waveforms Figure 2. Duty Cycle Waveform Cycle Timing (DC = t1A/t1B) t1A t1B SSCLK Figure 3. Output Rise/Fall Time Waveform VDD SSCLK 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 4. Output Enable/Disable Timing Waveforms VDD 0V VIL VIH OUTPUT ENABLE TOE2 SSCLK (Asynchronous) TOE1 High Impedance Document #: 001-07313 Rev. *A Page 5 of 8 [+] Feedback CY25701 Informational Graphs [4] 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 0 20 40 60 80 100 120 Time (us) 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% Fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 68.5 68 67.5 67 66.5 66 65.5 65 64.5 64 63.5 0 20 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 67.5 67 66.5 Fnominal Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 66 65.5 65 64.5 40 60 80 100 120 Time (us) 140 160 180 200 Fnominal 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Ordering Information Part Number Lead-free (Pb-free) CY25701FLXCT[5] CY25701FLXIT[5] CY25701LXCZZZT[6] CY25701LXIZZZT[6] Actual Marking[7] 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel CY25701FLX* Marketing Part Number (CY25701) F=Field Programmable Package Description Product Flow Commercial, -20 to 70C Industrial, -40 to 85C Commercial, -20 to 70C Industrial, -40 to 85C CY25701LX* Marketing Part Number (CY25701) L = LCC CY L X Pin 1 mark L = LCC X = Pb free 2 * Temp 5 7 0 1 F C X Pin 1 mark X = Pb free Y * Temp 2 z 5 z 7 z 0 1L Y WW YWW = Date Code (Year & WW) Y WW zzz = Programmable Dash Code YWW = Date Code (Year & WW) Notes 4. The "Informational Graphs" are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages 4 and 5 for device specifications. 5. "FLX" suffix is used for products programmed in field by Cypress Distributors. 6. "ZZZ" denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data is received from the customer. 7. Temp can be C (Com'l) or I (Industrial). Document #: 001-07313 Rev. *A Page 6 of 8 [+] Feedback CY25701 Package Drawings and Dimensions 4-Lead (5.0x3.2mm) Ceramic LCC LZ04A DIMENSIONS IN MM GENERAL TOLERANCE: 0.15MM 0.70 1.30 Max SIDE VIEW 5.0 0.80 1.20 3.2 #3 #2 #4 #1 2.90 2.50 TOP VIEW BOTTOM VIEW 001-02743-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-07313 Rev. *A Page 7 of 8 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY25701 Document History Page Document Title: CY25701 Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option Document Number: 001-07313 REV. ** *A ECN NO. 442944 487736 Issue Date See ECN See ECN Orig. of Change RGL New data sheet KKVTMP Added Industrial temp Description of Change Document #: 001-07313 Rev. *A Page 8 of 8 [+] Feedback |
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